"Top Picks in VLSI Test and Reliability” (TPTR) is a workshop that collects and presents the most impactful publications, keynotes and invited presentations in the past 6 years in the areas of VLSI test and reliability.

For this year’s edition, the workshop is organized in two tracks:

1. The most impactful publications from the past six years in the areas of VLSI test and reliability, as last year.

2. The most impactful keynotes and invited presentations from the past six years, without an associated publication, in the same areas.

All articles in conferences and journals published from 2018 until the submission deadline are eligible for track 1.

Keynotes or invited talks from an IEEE TTTC-sponsored conference from 2018 until the submission deadline are eligible for track 2.

The two submission categories will be evaluated separately.

Submission: TPTR accepts self-nominations by authors in the form of a one-page letter. The authors should summarize and highlight the key ideas and contributions of the presentation or publication, describe the influence on ongoing research in the field, and state the potential to positively impact the microelectronics industry in the long term.

Review: submitted abstracts will be reviewed by a committee of renowned experts in the field and will be shortlisted.Presentation: an author of each shortlisted publication must attend the workshop in person for a presentation showcasing its influence and impact. The presentation should be more than just replicating the original one. Authors should ensure that 30- 40% of the allocated time is dedicated to highlighting its influence on ongoing research in the field and its potential to impact the microelectronics industry.

Final selection: the same committee (or a subset of it) will also attend the workshop to select a final list of Top Picks, which will then be invited for submission to an IEEE Design & Test special issue. The submission should not repeat or reword the original publication or presentation; it should be an extended version with new material.

Important dates:

• Submission: September 01, 2024
• Notification: October 01, 2024

Organizing committee

Venue

Co-located with IEEE International Test Conference 2024 - November 7-8, 2024, San Diego, California, USA

Contact

Jyotika Athavale

Email: jyotika.a.athavale@gmail.com

Marcello Traiola

Email: marcello.traiola@inria.fr