Home
EPiC Series
Kalpa Publications
Preprints
For Authors
For Editors
Author
:
Pinniboyina Anand Venkat Seshu Babu
Publications
Implementation of 24 Bit Multiplier Using Parallel Multiplication with Sorting Based Binary Counters for VLSI Applications
Pinniboyina Anand Venkat Seshu Babu
and
K. Rajasekhar
EasyChair Preprint 8653
Keyphrases
24 bit multiplier
,
approximate 4:2 compressor
,
Binary counters
,
one-hot code
,
sorting network
.
Copyright © 2012-2025 easychair.org. All rights reserved.
