Download PDFOpen PDF in browserDesign and Simulation of Non-Inverting and Inverting Mixed Logic 2x4 Decoder Using Mentor Graphics 16nm Technology15 pages•Published: August 6, 2024AbstractPower reduction is one of the major development challenges of this period. In high performance digital frameworks, such as microchips, DSPs, and other applications, low power circuit designs are a requested feature. The primary factors taken into account when comparing any circuit or design are power and speed. When proposing any new design, designers should keep in mind the very impressive but declining chip area. 2x4 Decoder Binary inputs are converted to associated output bits in a pattern using 12 T. A new 2x4 decoder In this work, area optimization with the use of 12T is suggested. The 2:4 decoder is also executed using CMOS logic. The new design and CMOS logic are evaluated in terms of delay and power. Compared to CMOS logic architecture, which typically operates at 0.8V, the new 2x4 decoder design is optimized for power at a rate of 60.72%. PMOS of width (Wp)=64n& length(Ln)=16n,NMOS of width (Wn)=32n & length (Ln)=16n,Fan-out=1, and Wp/Wn=1, after that the designs are assessed at 0.8V with 16nm Mentor Tanner Tool has been used to validate the suggested procedure.Keyphrases: 16nm technology, decoder, low power modified mixed logic design, mentor graphics In: Rajakumar G (editor). Proceedings of 6th International Conference on Smart Systems and Inventive Technology, vol 19, pages 288-302.
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