CHOICE – A Tunable PUF-Design for FPGAs

EasyChair Preprint 6297

Abstract

FPGA-based Physical Unclonable Functions (PUFs) have emerged as a viable alternative to permanent key storage by turning inaccuracies during the manufacturing process of a chip into a unique, FPGA-intrinsic secret. However, many fixed PUF designs may suffer from unsatisfactory statistical properties in terms of uniqueness, uniformity, and robustness. Moreover, a PUF signature may alter over time due to aging or changing operating conditions, rendering a PUF insecure in the worst case. As a remedy, we propose CHOICE, a novel class of FPGA-based PUF designs with tunable uniqueness and reliability characteristics. By the use of addressable shift registers available on an FPGA, we show that a wide configuration space for adjusting a device- specific PUF response is obtained without any sacrifice of randomness. In particular, we demonstrate the concept of address-tunable propagation delays, whereby we are able to increase or decrease the probability of obtaining ’1’s in the PUF response. Experimental evaluations on a group of six 28 nm Xilinx Artix-7 FPGAs show that CHOICE PUFs provide a large range of configurations to allow a fine-tuning to an average uniqueness between 49% and 51%, while simultaneously achieving bit error rates below 1.5%, thus outperforming state-of-the-art PUF designs. Moreover, with only a single FPGA slice per PUF bit, CHOICE is one of the smallest PUF designs currently available on FPGAs.

Keyphrases: FPGA, Hardware-oriented security, PUF, Physical Unclonable Function, Security, cryptographic key, hardware/software co-design

@booklet{EasyChair:6297,
  author    = {Franz-Josef Streit and Paul Krüger and Andreas Becher and Jens Schlumberger and Stefan Wildermann and Jürgen Teich},
  title     = {CHOICE – A Tunable PUF-Design for FPGAs},
  howpublished = {EasyChair Preprint 6297},
  year      = {EasyChair, 2021}}