Getting started on Co-Emulation: Why and How to Transition your Design and UVM Testbench to an Emulator

EasyChair Preprint 614, version 2

Abstract

As we move to more complex and intricate designs, time spent in testing is ever crucial. With several avenues to test our design, we have to pick and choose best ways to optimize the overall time spent on testing. In our endeavor to move some test benches and designs to Emulation, we learnt several things that could be optimized from TestBench (TB) setup, Design changes to even SVA changes to achieve better simulation performance.

We also identified the kinds of tests and the nature of test benches to run on Emulation that would give the most ROI.

In this paper, we start with an overview and then boil down to some code samples. Then we’ll dig into things to be mindful of, in making effective use of the emulator platform.

Keyphrases: Coding Guideline, SystemVerilog, UVM, co-emulation, sce-mi2

@booklet{EasyChair:614,
  author    = {Jigar Savla},
  title     = {Getting started on Co-Emulation: Why and How to Transition your Design and UVM Testbench to an Emulator},
  howpublished = {EasyChair Preprint 614},
  year      = {EasyChair, 2018}}