CSR2: A New Format for SIMD-accelerated SpMV

EasyChair Preprint 2848

Abstract

SpMV (Sparse matrix vector multiplication) has attracted the attention of researchers in related fields at home and abroad. Of course, improving SpMV performance has also been a research hot spot for researchers in related fields. In this paper, we propose a new sparse matrix storage format CSR2 (Compressed Sparse Row 2) suitable for SIMD (Single Instruction Multiple Data)-accelerated SpMV. First, the format operation of CSR2 is easy to implement, and has low overhead of conversion. Second, CSR2 is a new single format and suitable for use on processor platforms with SIMD vectorization. We compare the SpMV algorithm based on CSR2 with the one based on the current most advanced single format CSR5 (Compressed Sparse Row 5) on two mainstream high-performance processors: Intel Core i7-7700HQ CPU and Intel Xeon CPU E5-2670 v3. We choose 10 sets of regular matrices and 3 sets of irregular matrices to be used as benchmark suit. Experiments show that for the 13 sets of regular and irregular matrices in the benchmark suit, CSR2 has an average performance improvement of more than 50% compared to CSR5 (up to 125% on Intel Core i7-7700HQ CPU and 303% on Intel Xeon CPU E5-2670 v3). For applications with multiple iterations in reality, using our CSR2 can bring low-overhead format conversion and high-throughput computing performance.

Keyphrases: CPU, CSR2, CSR5, SIMD vectorization, SpMV, Storage Formats

@booklet{EasyChair:2848,
  author    = {Haodong Bian and Jianqiang Huang and Runting Dong and Lingbin Liu and Xiaoying Wang},
  title     = {CSR2: A New Format for SIMD-accelerated SpMV},
  howpublished = {EasyChair Preprint 2848},
  year      = {EasyChair, 2020}}